Oct 22

Seminar: Soultana Ellinidou “The networking side of Interconnect” (Oct 29, 2019)

Oct 29, 2019 – 12.30 – room P.2NO8.08

Speaker: Soultana Ellinidou (ULB)

Title: “The networking side of Interconnect”
Short abstract: “Since fifty years, the number of transistors that was able to fit into a single piece of silicon increased in a predictable way known as Moore’s law. This had as a result the digital evolution of minicomputers to PCs, afterwards to smartphones and to cloud, by placing more and more transistors into each generation of their microchip and simultaneously making them more powerful and able to support the dynamic nature of today’s applications (for example in automotives and avionics). However the design and the validation of different architectures have been very well explored in literature, the interconnect fabric connecting the IP blocks of the entire System on Chip (Ship) must be equally explored in order to enable the properly distribution of the data within the system. As SoC grew in numbers of IP blocks, busses and crossbars interconnects revealed their limitations. Hence in the early 2000s, Network on chip (NoC) interconnect introduced as an on-chip packet switching micro-network in order to provide Quality of Service (QoS). Unfortunately due to high structural and functional complexity of NoC, researches start searching alternatives. In this presentation, we will present and evaluate the Software Defined Network on Chip (SDNoC), which is an NoC alternative by focusing on networking, routing and security aspects of it.”